1. Field of the Invention
This invention relates to the field of integrated circuit design, and in particular to programmable devices.
2. Description of Related Art
Programmable integrated circuits are common in the art, wherein the operation of the circuit is based on the contents of memory cells. Typically, the programming comprises a sequence of instructions, or a set of data, or a combination of both. The instructions may be, for example, object code for an embedded processor, and the data may be, for example, the values for a look-up table in a programmable logic device, or, the desired state of switch elements in a field-programmable gate array, and so on. For ease of reference, the terms xe2x80x9cprogramxe2x80x9d, xe2x80x9cprogram dataxe2x80x9d and xe2x80x9ccodexe2x80x9d as used herein includes instructions and data, and any combination thereof.
The program is typically xe2x80x9cdownloadedxe2x80x9d from a programming device, such as a desktop computer. The programming device asserts a control signal to place the programmable device into a reception mode, and communicates the content of the program as a sequence of location/code pairs. The location identifies the individual programmable element within the programming device that is being programmed, and the code identifies the value that the programmable element receives. In the reception mode, the programmable device places the received code at the specified location. In some devices, the location argument can be implicit: upon receipt of the control signal, the programmable device places the code at a default start location, and at sequential locations thereafter.
Depending upon the architecture of the programmable device, the reprogramming of the programmable device can be incremental, allowing for select locations to be reprogrammed, or total, requiring all locations to be reprogrammed. In most cases, additional information is also provided to facilitate the programming or reprogramming, such as checksums, error correcting sums, and so on. These and other programming techniques are common in the art.
The downloading of a program onto a programmable device typically renders the device inoperative while the program is being downloaded. A variety of techniques are available to minimize the inoperative time associated with the download of the program. The device and program may be partitioned into independent blocks, and the individual device blocks are loaded by the corresponding program block while that device block is not being utilized. This approach requires safeguards to assure that conflicts between the prior program and the new program do not arise among related blocks. An alternative approach is to provide multiple xe2x80x9cplanesxe2x80x9d of programmable elements within the system. In this approach, for example, a select-bit is used to select one of two planes of memory as an xe2x80x9cactivexe2x80x9d plane for system operation, the other plane being inactive, from the system""s perspective. Programming is effected by loading the inactive plane, then toggling the select-bit, making the newly programmed plane the currently active plane. The use of two programmable planes, however, effectively doubles the size of the area consumed by the programmable elements in the design. U.S. Pat. No. 5,778,439 discloses the use of multiple storage cells per memory element. In the referenced patent, incorporated herein by reference, one of the cells in each memory element is designated as an active storage, and the remaining cells (nominally 7) are inactive storage elements. Each of the inactive storage elements form a xe2x80x9cvirtualxe2x80x9d memory, that can be dynamically designated as the active storage, replacing the currently active storage. Each storage cell of each memory device in the referenced patent, however, comprises four to six transistors, thereby substantially increasing the size of the area consumed by these virtual memory device. Hybrid approaches are also viable. For example, buffering can be provided within the programmable device to minimize the effects of the relatively slow process of transferring the program from an external programming device by delaying the commencement of the actual programming of the programmable elements until a significant portion of the program is received. Because an internal transfer of the program can be effected more efficiently than a transfer from an external source, this buffering approach significantly reduces the overall inoperable duration, but a significant amount of buffering, and corresponding circuit area, must be provided to realize this gain.
It is an object of this invention to provide a programmable logic device that can be programmed, and reprogrammed, quickly. It is a further object of this invention to provide a programmable logic device that can be reprogrammed quickly that consumes minimal additional circuitry and circuitry area. It is a further object of this invention to provide an area efficient architecture for multi-plane programming applications.
These objects and others are achieved by providing a programmable cell having an externally loadable electrically erasable (EE) transistor cell that is configured to be independent of the currently active state of the programmed cell. When all of the EE cells are loaded with a new configuration, the contents of all of the EE cells are loaded into the corresponding programmable cells, preferably within one clock cycle. Because the entirety of the programmable cells can be pre-loaded with the new configuration, the time to effect a reconfiguration is one clock cycle. Because an EE cell is significantly smaller than a conventional four to six transistor storage cell, the area required to implement this single-clock-cycle reconfiguration capability is substantially less than traditional dynamically reprogrammable device configurations. In an alternative embodiment, multiple EE cells can be associated with each programmable cell, thereby allowing a multiple-configuration capability.